

//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
//            (C) COPYRIGHT 2008-2012 ARM Limited.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//------------------------------------------------------------------------------
// Version and Release Control Information:
//
// File Revision       : 133019
// File Date           :  2012-07-04 09:22:09 +0100 (Wed, 04 Jul 2012)
// Release Information : PL401-r0p1-00eac0
//------------------------------------------------------------------------------
// Purpose : AXI to ITB RTL
//------------------------------------------------------------------------------


//------------------------------------------------------------------------------
// Module Declaration
//------------------------------------------------------------------------------
module nic400_ib_tpv_gp_apb4_ib_axi_to_itb_ysyx_rv32
(
  //-----------
  // AXI input
  //-----------

  // AW Channel
  awid,
  awaddr,
  awlen,
  awsize,
  awburst,
  awlock,
  awcache,
  awprot,
  awregion,
  awvalid,
  awready,

  // B Channel
  bid,
  bresp,
  bvalid,
  bready,

  // AR Channel
  arid,
  araddr,
  arlen,
  arsize,
  arburst,
  arlock,
  arcache,
  arprot,
  arregion,
  arvalid,
  arready,

  // R Channel
  rid,
  rdata,
  rresp,
  rlast,
  rvalid,
  rready,


  //------------
  // ITB output
  //------------

  // A Channel
  awrite,
  aid,
  aaddr,
  alen,
  asize,
  aburst,
  alock,
  acache,
  aprot,
  aregion,
  avalid,
  aready,

  // D Channel
  dbnr,
  did,
  ddata,
  dresp,
  dlast,
  dvalid,
  dready,


  //-------------------------
  // Clock and reset signals
  //-------------------------
  aclk,
  aresetn
);


//------------------------------------------------------------------------------
// Port definitions
//------------------------------------------------------------------------------

  //-----------
  // AXI input
  //-----------

  // AW Channel
  input  [3:0]          awid;                  // Write address ID
  input  [31:0]         awaddr;                // Write address
  input  [7:0]             awlen;                 // Write address length field
  input  [2:0]          awsize;                // Write address size
  input  [1:0]          awburst;               // Write address burst length
  input                    awlock;                // Write address lock
  input  [3:0]          awcache;               // Write address cache field
  input  [2:0]          awprot;                // Write address prot field
  input  [3:0]          awregion;              // Write address region selection
  input                 awvalid;               // Write address valid
  output                awready;               // Write address ready

  // B Channel
  output [3:0]          bid;                   // B response ID
  output [1:0]          bresp;                 // B response status
  output                bvalid;                // B response valid
  input                 bready;                // B response ready

  // AR Channel
  input  [3:0]          arid;                  // Read address ID
  input  [31:0]         araddr;                // Read address
  input  [7:0]             arlen;                 // Read address length
  input  [2:0]          arsize;                // Read address size
  input  [1:0]          arburst;               // Read address burst length
  input                    arlock;                // Read address lock
  input  [3:0]          arcache;               // Read address cache field
  input  [2:0]          arprot;                // Read address prot field
  input  [3:0]          arregion;              // Read address region selection
  input                 arvalid;               // Read address valid
  output                arready;               // Read address ready

  // R Channel
  output [3:0]          rid;                   // Read data ID
  output [31:0]         rdata;                 // Read data
  output [1:0]          rresp;                 // Read data response status
  output                rlast;                 // Read data last
  output                rvalid;                // Read data valid
  input                 rready;                // Read data ready


  //------------
  // ITB output
  //------------

  // A Channel
  output                awrite;                // R/W address flag
  output [3:0]          aid;                   // R/W address ID
  output [31:0]         aaddr;                 // R/W address
  output [7:0]          alen;                  // R/W address length field
  output [2:0]          asize;                 // R/W address size
  output [1:0]          aburst;                // R/W address burst length
  output                   alock;                 // R/W address lock
  output [3:0]          acache;                // R/W address cache field
  output [2:0]          aprot;                 // R/W address prot field
  output [3:0]          aregion;               // R/W address region selection
  output                avalid;                // R/W address valid
  input                 aready;                // R/W address ready

  // D Channel
  input                 dbnr;                  // R/B flag
  input  [3:0]          did;                   // R/B ID
  input  [31:0]         ddata;                 // Read data / B user
  input  [1:0]          dresp;                 // R/B response status
  input                 dlast;                 // Read data last
  input                 dvalid;                // R/B valid
  output                dready;                // R/B ready


  //-------------------------
  // Clock and reset signals
  //-------------------------
  input                 aclk;                  // Main clock
  input                 aresetn;               // Main reset


//------------------------------------------------------------------------------
// Internal signals
//------------------------------------------------------------------------------

  // A Channel
  wire                  awrite_i;              // Internal A channel write flag
  wire                  awrite_nxt;            // Next A channel write flag
  reg                   awrite_reg;            // Last A channel write flag
  wire                  avalid_i;              // Internal A channel valid
  reg                   avalid_reg;            // Last A channel valid
  reg                   aready_reg;            // Last A channel ready


//------------------------------------------------------------------------------
// Start of code
//------------------------------------------------------------------------------

  // A Channel
  always @(posedge aclk or negedge aresetn)
    begin : p_a_seq
      if (!aresetn)
        begin
          awrite_reg <= 1'b0;
          avalid_reg <= 1'b0;
          aready_reg <= 1'b0;
        end
      else
        begin
          awrite_reg <= awrite_nxt;
          avalid_reg <= avalid_i;
          aready_reg <= aready;
        end
    end // p_a_seq

  assign awrite_nxt = (avalid_i && aready) ? awrite_i
                        : ((avalid_i && (~avalid_reg || aready_reg)) ? ~awrite_i
                          : awrite_reg);

  assign awrite_i = awvalid & ~(awrite_reg & arvalid);

  assign awrite = awrite_i;

  assign {aid,
          aregion,
          aaddr,
          alen,
          asize,
          aburst,
          alock,
          acache,
          aprot} = awrite_i ?
         {awid,
          awregion,
          awaddr,
          awlen,
          awsize,
          awburst,
          awlock,
          awcache,
          awprot} :
         {arid,
          arregion,
          araddr,
          arlen,
          arsize,
          arburst,
          arlock,
          arcache,
          arprot};

  assign avalid_i = awvalid | arvalid;

  assign avalid = avalid_i;

  assign awready = aready & awrite_i;
  assign arready = aready & ~awrite_i;


  // D Channel

  assign bresp = dresp;

  assign bid = did;
  assign rid = did;

  assign {rdata,
          rresp,
          rlast} =
         {ddata,
          dresp,
          dlast};

  assign bvalid = dvalid & dbnr;

  assign rvalid = dvalid & ~dbnr;

  assign dready = (dbnr & dvalid) ? bready : rready;


endmodule // nic400_ib_tpv_gp_apb4_ib_axi_to_itb_ysyx_rv32


//------------------------------------------------------------------------------
// End of File
//------------------------------------------------------------------------------

